NQVL:QSTD:Design: Accelerating Fault-Tolerant Quantum Logic (FTL)

The ability of quantum hardware to outperform classical hardware for tasks like computation, communication, and sensing is known as quantum advantage. Quantum advantage promises society-changing benefits including fundamentally secure communication, improved biomedical sensing, and breakthroughs in materials and drug design. To date, useful quantum advantage for computation has not been realized. Though there is reason to be optimistic for near term advances, it is widely accepted that useful quantum advantage in computing will require fault tolerance at scale – an advance that is still beyond the reach of current devices. This project aims to accelerate the development of fault-tolerant quantum computation by co-designing error correcting codes and the hardware that will run them. Currently, many quantum error-correcting (QEC) codes have been discovered, and their mathematical structures are becoming better understood. Meanwhile, hardware with a few logical qubits has been demonstrated and, in some cases, a small suppression of errors realized. However, the demands on hardware for current QEC codes are severe -- either enormous numbers of qubits are required or native gate error rates must be extremely low (often, both). By designing QEC codes to utilize the native gates and connectivity of the hardware, while simultaneously optimizing the hardware layout to support the QEC code, fault tolerance can be achieved with the minimum resource cost thereby delivering useful quantum advantage sooner. The FTL project develops the preliminary design of a 60 logical-qubit, fault-tolerant quantum computer based on a trapped-ion quantum charge-coupled device architecture. The system targets logical gate error rates below 10^{-5}, enabling reliable digital quantum simulation in the quantum advantage regime. The research integrates advances in high-fidelity trapped-ion qubits, scalable ion transport through multidimensional junctions, photonic control systems, and hardware-aware quantum error correction. Hybrid error-correction strategies dynamically combine encoded and unencoded operations to reduce overhead while preserving fault tolerance. A full software stack, including compilation and real-time control, is co-optimized with the hardware architecture. Experimental validation of key primitives, integrated photonics, junction transport, and finite-field qubit operation informs a comprehensive preliminary design package. The project delivers an openly developed blueprint for scalable fault-tolerant quantum computing and provides a testbed for benchmarking algorithms and error-correction methods across the quantum research community. This project advances the objectives of Quantum Information Science and Technology at NSF in response to the National Quantum Initiative Act for the continued leadership of the United States in QIS and its technology applications. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. NSF Award ID: 2547483 | Program: 01002728DB NSF RESEARCH & RELATED ACTIVIT,01002627DB NSF RESEARCH & RELATED ACTIVIT | Principal Investigator: Eric Hudson | Institution: University of California-Los Angeles, LOS ANGELES, CA | Award Amount: $2,000,000 View on NSF Award Search: https://www.nsf.gov/awardsearch/show-award/?AWD_ID=2547483 View on Research.gov: https://www.research.gov/awardapi-service/v1/awards/2547483.html