ERI: HYDRA: A Truly Heterogeneous Near-Memory Processing Architecture for Multimodal, Energy-Efficient Edge Computing.

This Engineering Research Initiation (ERI) grant will support fundamental research on improving versatile computing support within memory devices. The foundational knowledge from this research will enable the design and development of low-power, compact computing hardware for fast artificial intelligence (AI), cryptography, and other similar data-intensive computing within edge systems. Modern computers currently suffer from a memory bottleneck, where more than half of a system's energy is often spent simply moving data back and forth between the memory and the processor. A new generation of computers, known as ‘memory-centric processors’, aims to solve this problem by performing calculations within or near a memory device. However, current designs struggle to match the capability and versatility of mainstream processors and introduce additional complexity and challenges that significantly compromise the viability of these innovations in real-world applications. The proposed research aims to design a new memory-centric processor that simplifies the integration of versatile computing abilities within the memory device to support AI, data security, and other data-intensive tasks with superior efficiency. The project will also support sustained educational development and outreach activities geared towards increasing Science, Technology, Engineering, and Mathematics (STEM) enrollment and training high-skilled engineers within the Boise Metropolitan Area. Additionally, the simulation toolchain, software, and technical knowledge developed as part of this project will be publicly released to make them accessible to the broader scientific community. The overarching goal of this proposal is to design and develop an architectural and control fabric of a hierarchical, heterogeneous near-memory computing within Dynamic Random Access Memory (DRAM). This fabric will utilize the internal data bandwidth of DRAM to facilitate efficient parallel and heterogeneous computing while minimizing the data bandwidth bottlenecks and data movement overheads of computing. The foundational research will provide the critical insights needed to overcome dataflow and control-level challenges in a holistic manner, offering a viable solution for future heterogeneous near-memory computing that supports multimodal AI, cryptography, and other data-intensive workloads in edge systems. In pursuit of this goal, the proposed research will make two primary contributions: i) developing an architectural framework featuring diverse groups of near-memory Processing Units (PUs) spatially distributed across the memory organization, featuring a shared, quasi-homogeneous control architecture, and ii) developing a hardware-driven instruction routing and internalized data access mechanism within the DRAM to sustain parallel, distributed computing within DRAM while avoiding datapath congestions. The project will be designed, optimized, and evaluated using a multi-level simulation framework spanning circuit, Register Transfer Level (RTL), architecture, and system-level abstractions, and it will also be prototyped and verified on an FPGA platform. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. NSF Award ID: 2552607 | Program: 01002627DB NSF RESEARCH & RELATED ACTIVIT | Principal Investigator: Purab Ranjan Sutradhar | Institution: Boise State University, BOISE, ID | Award Amount: $199,695 View on NSF Award Search: https://www.nsf.gov/awardsearch/show-award/?AWD_ID=2552607 View on Research.gov: https://www.research.gov/awardapi-service/v1/awards/2552607.html