CAREER: System-Technology Co-Optimization for 3-D ICs With Hierarchical Digital Twins

This award supports research on three-dimensional (3D) chip design methods that advance national prosperity by enabling more capable and energy-efficient computing systems. Modern software applications, such as Artificial Intelligence (AI) large-language models, require orders-of-magnitude improvements in performance and energy efficiency beyond what traditional transistor scaling can deliver, and a growing share of energy is wasted shuttling data between processors and memory rather than performing useful computation. 3D chip integration can overcome this challenge by co-locating computation and memory within a single chip footprint. However, it introduces a combinatorial design landscape with tightly coupled tradeoffs across devices, interconnects, packaging, thermal management, and overall hardware architecture. This project will develop a hierarchical System-Technology Co-Optimization (STCO) framework powered by fast and accurate virtual models of devices, circuits, packaging, and applications. These models will enable rapid exploration of 3D chip design alternatives and, uniquely, will derive required 3D chip technology targets directly from application-level performance needs. The outcome will be new design methods, open-source design tools, and hardware prototypes that enable more energy-efficient 3D chip computing systems, strengthening U.S. leadership in advanced semiconductor technologies and workforce development. Education activities will integrate 3D chip design modules into hands-on fabrication and advanced chip-design courses, establish technician training in semiconductor manufacturing, and engage local K-12 students through interactive outreach programs. The technical goal is a hierarchical system-technology co-optimization (STCO) toolchain that jointly explores device choices, packaging, and chip architecture for 3D integrated circuits. The project will (1) build calibrated models for logic and memory device technologies used in 3D stacks by combining physics-based and data-driven modeling, calibrated with experimental measurements where available; (2) model and optimize 3D packaging, including high-density vertical wiring networks and thermal structures that improve heat spreading between stacked layers; and (3) integrate these device and packaging models with workload and architecture descriptions using hierarchical intermediate representations that enable fast design-space exploration. The STCO toolchain will map applications onto candidate 3D chip architectures and estimate power and performance in minutes, and will also derive target technology parameters, such as vertical connection density and transistor drive current, from application-level performance objectives using symbolic modeling and constrained optimization. The framework will be validated with prototype test chips fabricated using a foundry-based monolithic 3D process in which chip layers are built sequentially on the same wafer. Results will be disseminated through open-source tools, benchmarks, and course materials. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. NSF Award ID: 2544278 | Program: 01002930DB NSF RESEARCH & RELATED ACTIVIT,01002627DB NSF RESEARCH & RELATED ACTIVIT,01003031DB NSF RESEARCH & RELATED ACTIVIT | Principal Investigator: Tathagata Srimani | Institution: Carnegie Mellon University, PITTSBURGH, PA | Award Amount: $367,934 View on NSF Award Search: https://www.nsf.gov/awardsearch/show-award/?AWD_ID=2544278 View on Research.gov: https://www.research.gov/awardapi-service/v1/awards/2544278.html