CAREER: Monolithic 3D Oxide Semiconductor Nanoelectronics for Energy-Efficient Computing

We live in an era of unprecedented data explosion, where autonomous intelligent systems constantly generate and process enormous amounts of data in real-time. For example, today a single autonomous vehicle can generate nearly 40 terabytes of sensor data per hour, which is equivalent to streaming 6,000 Netflix movies simultaneously. Interpreting such massive data with artificial intelligence (AI) requires computing hardware that is both extremely fast and highly energy efficient while providing large storage capability. However, today’s computer chips face fundamental limitations. Most chips are built like a flat city, where different components responsible for computing, storage, and communication sit side by side. This arrangement forces large amounts of data to travel long distances between different parts of a system, consuming significant energy and slowing performance. One promising solution is to build computer chips more like a multi-story building, where different layers of electronics are stacked vertically. This three-dimensional (3D) design can dramatically shorten communication distances, enabling faster operation and lower energy consumption. Achieving this vision requires new types of electronic switches, called transistors, that can be manufactured at low temperatures so they can be safely built on top of existing circuits. This project studies a new class of materials that can enable such vertically stacked chips while maintaining high performance and extremely low energy consumption. The goal of this CAREER proposal is to advance the science of amorphous oxide semiconductor (AOS) nanoelectronics and enable their use in 3D integrated systems. The research will investigate four fundamental aspects: (1) scaling limits of AOS transistors with stackable non-planar geometry, (2) vertical 3D integration, (3) fundamental understanding of AOS device physics including transport, reliability and thermal, and (4) AI-driven acceleration of AOS technology development. The project will first demonstrate stacked nanosheet AOS transistors and experimentally study their electrical, thermal, and reliability characteristics. Detailed characterization will be used to uncover transport mechanisms, self-heating effects, and degradation behavior in ultra-scaled devices. Based on these insights, physics-based transistor models will be developed and integrated into compact models suitable for circuit-level simulation. These models will enable multi-scale simulations to evaluate device performance and system-level implications in vertically integrated architectures. Finally, the project will develop a digital twin framework for AOS nanoelectronics that integrates fabrication, characterization, modeling, and simulation within a unified data-driven platform to accelerate design space exploration, significantly reducing experimental cost and accelerating technology optimization. Together, these efforts will establish the fundamental device physics, predictive modeling tools, and data-driven methodologies needed to enable scalable AOS technologies for next-generation energy-efficient computing systems. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. NSF Award ID: 2541681 | Program: 01002627DB NSF RESEARCH & RELATED ACTIVIT | Principal Investigator: Sourav Dutta | Institution: University of Texas at Dallas, RICHARDSON, TX | Award Amount: $501,234 View on NSF Award Search: https://www.nsf.gov/awardsearch/show-award/?AWD_ID=2541681 View on Research.gov: https://www.research.gov/awardapi-service/v1/awards/2541681.html