CAREER: Error-Resilient Algorithmic Design for Emerging Hardware Technologies

Running artificial intelligence workloads requires vast amounts of memory and energy, motivating a new generation of memory and transistor technologies that pack more storage closer to compute and operate at lower power. These emerging devices are promising candidates for accelerating AI, but they experience data corruption at rates far higher than conventional hardware, making them unreliable without costly error-correction techniques that erase their efficiency advantage. This project develops software tools and mathematical foundations that allow AI algorithms to be written so that they are naturally tolerant of such hardware errors, making these devices viable for real-world use without requiring error correction. The educational plan trains the next generation of students from computer science and electrical engineering to collaborate across the hardware/software boundary, addressing a critical workforce gap for the design of next-generation AI computing systems. The technical objective of this project is to establish exchangeability - a statistical symmetry property present in hyperdimensional computing, a naturally error-resilient computational model - as a principled foundation for error-resilient algorithm design across a broader class of computations, including machine learning inference and optimization. The central hypothesis is that exchangeability is more widespread than previously recognized, and that programs possessing this property can tolerate hardware-induced data corruption without sacrificing correctness. This project pursues two research thrusts. In the first, a programming language is developed for expressing and analyzing exchangeable programs, characterizing which AI and optimization algorithms possess this property. In the second, a compiler is developed that automatically optimizes such programs for performance and error resilience, evaluated in simulation across realistic hardware error models. The educational plan is integrated with these thrusts through "Hardware Anywhere" open-source projects that engage computer science and mathematics students in hardware design problems, and through coursework that gives students hands-on experience developing software optimizations for emerging hardware platforms. This work opens new connections between statistics, programming languages, and AI systems, and will be among the first to establish exchangeability as an exploitable computational property for program optimization. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. NSF Award ID: 2540782 | Program: 01002930DB NSF RESEARCH & RELATED ACTIVIT,01003031DB NSF RESEARCH & RELATED ACTIVIT,01002627DB NSF RESEARCH & RELATED ACTIVIT | Principal Investigator: Sara Achour | Institution: Stanford University, STANFORD, CA | Award Amount: $414,320 View on NSF Award Search: https://www.nsf.gov/awardsearch/show-award/?AWD_ID=2540782 View on Research.gov: https://www.research.gov/awardapi-service/v1/awards/2540782.html