CAREER: Algorithm-Hardware Cross-Layer Design for High-Performance Scientific Data Compression

High-performance computing (HPC) enables scientists to simulate and study complex natural phenomena that are difficult or impossible to observe directly, including climate change, astrophysical evolution, fluid motion, and biological processes. These simulations generate enormous volumes of data, often reaching petabyte or even exabyte scales, posing severe challenges for storage, data transfer, and I/O performance in HPC systems. While scientific data compression has become essential for enabling efficient use of computing infrastructure and for helping researchers analyze and share simulation results more effectively, a widening gap exists between the intensive computational workloads of contemporary data compression and the insufficient support of existing general-purpose hardware. This project addresses this gap by developing an innovative algorithm-hardware cross-layer framework that synergistically integrates AI and neural learning methods across multiple compression stages, significantly enhancing the reliability, quality, and overall performance of data compression. The completion of this research will improve the usability of large-scale simulations and strengthen the computing infrastructure supporting research across various scientific domains. This project will develop an algorithm-hardware co-design for high-performance AI- and neural learning-integrated scientific data compression. The research has three closely connected components. First, it will establish algorithmic principles for novel multi-mode neural compression by integrating AI and neural models with classical scientific compression to improve compression quality, reliability, and computational efficiency for diverse scientific data requirements. Second, it will design specialized hardware support for the distinctive computation and dataflow patterns of AI-fused neural compression, including new architectural primitives and microarchitectural optimizations to improve throughput, energy efficiency, and system utilization. Third, it will develop automated methods for jointly designing, mapping, and evaluating compression algorithms and hardware under diverse application requirements, architectural constraints, and I/O budgets. The software and hardware techniques of this project will be implemented via FPGAs and evaluated for real-world scientific simulations on HPC systems. The research outcomes will advance multiple fields, including HPC, AI, machine learning, computing architecture, and data-intensive scientific research. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. NSF Award ID: 2544246 | Program: 01003031DB NSF RESEARCH & RELATED ACTIVIT,01002627DB NSF RESEARCH & RELATED ACTIVIT,01002930DB NSF RESEARCH & RELATED ACTIVIT | Principal Investigator: Miao Yin | Institution: University of Texas at Arlington, ARLINGTON, TX | Award Amount: $347,035 View on NSF Award Search: https://www.nsf.gov/awardsearch/show-award/?AWD_ID=2544246 View on Research.gov: https://www.research.gov/awardapi-service/v1/awards/2544246.html